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19-7685; rev 2; 8/16 general description the max14720/MAX14750 are compact power-management solutions for space-constrained, battery-powered applications where size and efficiency are critical. both devices integrate a power switch, a linear regulator, a buck regulator, and a buck-boost regulator. the max14720 is designed to be the primary power- management device and is ideal for either non-rechargeable battery (coin-cell, dual alkaline) applications or for rechargeable solutions where the battery is removable and charged separately. the device includes a button monitor and sequencer. the MAX14750 works well as a companion to a charger or pmic in rechargeable applications. it provides direct pin control of each function and allows greater flexibility for controlling sequencing. the devices include two programmable micro-i q , high- efficiency switching converters: a buck-boost regulator and a synchronous buck regulator. these regulators feature a burst mode for increased efficiency during light- load operation. the low-dropout linear regulator has a programmable output. it can also operate as a power switch that can disconnect the quiescent load of system peripherals. the devices also include a power switch with battery- monitoring capability. the switch can isolate the battery from all system loads to maximize battery life when not operating. it is also used to isolate the battery-impedance measurements. this switch can operate as a general- purpose load switch as well. the max14720 includes a programmable power controller that allows the device to be configured either for use in applications that require a true off state or for always-on applications. this controller provides a delayed reset signal, voltage sequencing, and customized button timing for on/off control and recovery hard reset. both devices also include a multiplexer for monitoring the power inputs and outputs of each function. these devices are available in a 25-bump, 0.4mm pitch, 2.26mm x 2.14mm wafer-level package (wlp) and operate over the -40c to +85c extended temperature range. benefts and features extended system battery use time ? micro-i q 250mw buck-boost regulator - input voltage from 1.8v to 5.5v - output voltage programmable from 2.5v to 5v - 1.1a quiescent current - programmable current limit ? micro-i q 200ma buck regulator - input voltage from 1.8v to 5.5v - output voltage programmable from 1.0v to 2.0v - 0.9a quiescent current ? micro-i q 100ma ldo - input voltage from 1.71v to 5.5v - output programmable from 0.9v to 4.0v - 0. 9a quiescent current - confgurable as load switch extend product shelf-life ? battery seal mode (max14720) - 120na battery current ? power switch on-resistance - 250m (max) at 2.7v - 500m (max) at 1.8v ? battery impedance detector easy-to-implement system control ? confgurable power mode and reset behavior (max14720) - push-button monitoring to enable ultra-low power shipping mode - disconnects all loads from battery and reduces leakage to less than 1a - power-on reset (por) delay and voltage sequencing ? individual enable pins (MAX14750) ? voltage monitor multiplexer ? i 2 c control interface applications wearable medical devices wearable fitness devices portable medical devices ordering information appears at end of data sheet. max14720/MAX14750 power-management solution
(voltages referenced to gnd.) bin, lin, sda, scl, swin, ben, swout, swen, len, hven, hvin, hvout, mon, cap, v cc , mpc, kin, rst, kout ................................... -0.3v to +6.0v hvilx ...................................................... -0.3v to v hvin + 0.3v hvolx ................................................ -0.3v to v hvout + 0.3v blx, bout .............................................. -0.3v to (v bin + 0.3v) lout ....................................................... -0.3v to (v lin + 0.3v) gnd ...................................................................... -0.3v to +0.3v continuous-current into hvin, bin, swin ................. 1000ma continuous-current into any other terminal ................ 100ma continuous power dissipation (multilayer board at +70c): 5x5 array 25-ball 2.26mm x 2.14mm 0.4mm pitch wlp (derate 19.07mw/c) ................................................... 1.525w operating temperature range .......................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ........................... -65c to +150c lead temperature (soldering 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c wlp junction-to-ambient thermal resistance ( ja ) ..... 52.43c/w (note 1) (v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics parameter symbol conditions min typ max units s upply current seal input current i seal seal mode, all functions disabled 0.12 1 a off input current i off no blocks enabled, no battery measurement active 1.2 2.8 a mon input current i mon no blocks enabled, no battery measurement active, mon enabled, monctr[2:0] = 000. 4 7.2 a switch input current i sw switch enabled, i swout = 0a 1.2 2.8 a ldo input current i ldo ldo enabled, i lout = 0a 2.1 4.4 a ldo enabled, lin uvlo enabled, i lout = 0a 2.4 4.8 ldo enabled, switch mode, i lout = 0a 1.5 3.2 buck input current i buck buck enabled, i bout = 0a 2 4.1 a buck enabled, bin uvlo enabled, i bout = 0a 2.2 4.5 buck-boost input current i bckbst buck-boost enabled, i hvout = 0a, v hvout = 4v 2 4.7 a buck-boost enabled, bin uvlo enabled, i hvout = 0a, v hvout = 4v 2.3 5 max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 3 electrical characteristics (continued) parameter symbol conditions min typ max units on input current i on ldo, buck, and buck-boost enabled; bin uvlo and lin uvlo enabled; i swout = i lout = i bout = i hvout = 0a 4.4 8.3 a power sequence boot time t boot max14720 9.9 11 12.1 ms MAX14750 21.6 24 26.4 ms reset time t rst max14720 72 80 88 ms power switch input voltage range v swin v swin v cc 1.8 5.5 v quiescent supply current i q_sw i swout = 0a 0.05 0.09 a switch on-resistance r on_sw i swout = 200ma 0.16 0.25 ? v swin = 1.8v, i swout = 200ma 0.27 0.5 maximum output current i swout_max 200 ma turn-on time t on_sw i swout = 0ma, c swout = 100f, time from 10% to 90% of v swin , swsoftstart = 0 0.65 ms i swout = 0ma, c swout = 100f, time from 10% to 90% of v swin , swsoftstart = 1 13.8 ms short-circuit current limit i shrt_sw v swout = gnd, swsoftstart = 0 200 460 700 ma soft-start current limit i sstr_sw v swout = gnd, swsoftstart = 1 9 25 54 ma thermal-shutdown threshold t shdn_sw t j rising 150 c thermal-shutdown hysteresis t shdn_hyst_sw 20 c buck boost converter (c out = 10f , l = 4.7f, unless otherwise noted .) input voltage range v hvin 1.8 5.5 v quiescent supply current i q_boost v hvout = 4v, i hvout = 0a, bin uvlo disabled 1.1 2.6 a v hvout = 4v, i hvout = 0a, bin uvlo enabled 1.3 3 a minimum input voltage startup v hvin_stup i load = 1ma, minimum input voltage for correct startup of the buck-boost 1.9 v max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 4 electrical characteristics (continued) parameter symbol conditions min typ max units maximum output operating power p maxhvout v hvin = 3v 250 mw output voltage v hvout 100mv step 2.5 5 v output accuracy acc hvout i hvout = 1ma, average output c out 10f -3 +3 % line regulation error v hvinreg_boost v hvin = 1.8v to 5.5v, i hvout = 10ua, v hvout = 4v, i set = 100ma -1 0.1 +1 %/v load regulation error v loadreg_boost v hvout = 4v, i hvout = 10a to 50ma, i set = 100ma 100 mv/a v hvout = 4v, i hvout = 10a to 100ma, i set = 100ma 310 mv/a line transient v linetran_bst v hvout = 4v, i set = 100ma, v hvin = v cc = 2.5v to 5v, 0.2s rise time 15 mv load transient v loadtran_bst i hvout = 0ma to 10ma, 200ns rise time, v hvout = 4v, i set = 100ma 9 mv i hvout = 0ma to 100ma, 200ns rise time, v hvout = 4v, i set = 100ma 31 mv oscillator frequency f osc_bst 1.78 2 2.25 mhz passive discharge pulldown resistance r pdl_bst 5 10 16 k? active discharge current i actdl_bst v hvin = 3v 6 19 38 ma turn-on time t on_boost time from enable to full current capability 100 ms uvlo on hvout v hvout_uvlo uvlo voltage on hvout rising 1.6 1.75 1.9 v uvlo threshold hysteresis v uvlo_hys 150 mv precharge current i pc_boost precharge current. v hvin = 1.8v, v hvout = 1.65v 4 6.5 9 ma startup input current i instup_bst input startup current. v hvin = 1.8v, v hvout = 1.6v 11 ma startup output current i ostup_bst output startup current. v hvin = 1.8v, v hvout = 5v 6.5 ma pulse mode input current limit i pls_in v hvout = 4v, v hvin < v hvout - 0.5v, f sw = f osc /10, i set = 100ma 6.6 ma max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 5 electrical characteristics (continued) parameter symbol conditions min typ max units pulse mode switching period ratio t ratio f osc /f sw , 128 steps 10 138 short-circuit peak current limit i shrt_boost v hvout = gnd. 0.4 1.1 1.9 a thermal-shutdown threshold t shdn_bst t j rising 150 c thermal-shutdown hysteresis t shdn_hyst_bst 21 c buck converter (c out = 10f, l = 2.2 h, unless otherwise noted. ) input voltage range v bin 1.8 5.5 v quiescent supply current i q_buck i bout = 0a 0.8 1.6 a i bout = 0a, bin uvlo enabled 1 2 i bout = 0a, buckmd[1:0] = 01 4.8 ma maximum operative output current i maxbout 250 ma output voltage v bout 25mv step 1 2 v output accuracy a cc_bout v bin = (v bout + 0.1v) or higher, i bout = 1ma; average output -3 +3 % dropout voltage v drop_buck i bout = 0a 95 120 mv line regulation error v linereg_buck v bin = from 2v to 5v, v bout = 1.2v 0.65 %/v load regulation error v loadreg_buck buckinteg = 1, i bout = 200ma 23 mv line transient v linetran_buck v bout = 1.2v, v bin = v cc : 2.0v to 5v, 1s rise time 50 mv load transient v loadtran_buck i bout = 0ma to 200ma, 200ns rise time 70 mv oscillator frequency f osc_bk 1.78 2 2.25 mhz passive discharge pull-down resistance r pdl_bk 5 10 16 k? active discharge current i actdl_bk 5.5 17 33 ma turn-on time t on_buck time from enable to full current capability; buckfst = 0 60 ms time from enable to full current capability; buckfst = 1 30 ms startup output current i stup_bk buckfst = 0 18 ma max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 6 electrical characteristics (continued) parameter symbol conditions min typ max units startup output current i stup_bk buckfst = 1 42 ma short-circuit peak current limit i shrt_buck v bout = gnd. 0.54 0.8 2.19 a thermal-shutdown threshold t shdn_buck t j rising 150 c thermal-shutdown hysteresis t shdn_hyst_buck 21 c ldo (c lout = 1f, unless otherwise noted. typical values are with i lout = 10ma, v lout = 2v) input voltage range v lin ldo mode 1.71 5.5 v switch mode 1.2 5.5 quiescent supply current i q_ldo i lout = 0a 0.9 1.9 a i lout = 0a, lin uvlo enabled 1.1 2.2 i lout = 0a, switch mode 0.3 0.5 quiescent supply current in dropout i q_ldo_drp i lout = 0a, v set = 2.8v 2.1 4.6 a maximum output current i lout_max v lin > 1.8v 100 ma v lin = 1.8v or lower 50 ma output voltage v lout 100mv step 0.9 4 v output accuracy acc ldo v lin = (v lout + 0.5v) or higher, i lout = 1ma -3.1 +3.1 % dropout voltage v drop_ldo v lin = v set = 2.7v, i lout = 100ma 100 mv line regulation error v linereg_ldo v lin = (v lout + 0.5 v) to 5.5v -0.5 +0.5 %/v load regulation error v loadreg_ldo v lin = 1.8v or higher, i lout = 100a to 100ma 0.001 0.005 %/ma line transient v linetran_ldo v lin = 4v to 5v, 200ns rise time 35 mv v lin = 4v to 5v,1s rise time 25 mv load transient v loadtran_ldo i lout = 0ma to 10ma, 200ns rise time 100 mv i lout = 0ma to 100ma, 200ns rise time 200 mv passive discharge pulldown resistance r pdl_ldo 4 10 18 k? active discharge current i actdl_ldo 5 20 40 ma max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 7 electrical characteristics (continued) parameter symbol conditions min typ max units switch mode resistance r on_ldo v lin = 1.8v, i lout = 50ma 1 ? v lin = 1.2v, i lout = 5ma 3 turn-on time t on_ldo i lout = 0ma , time from 10% to 90% of fnal regulation value 0.95 ms i lout = 0ma , time from 10% to 90% of v lin , switch mode 1.8 ms short-circuit current limit i shrt_ldo v lout = gnd 380 ma v lout = gnd, switch mode 370 ma thermal-shutdown threshold t shdn_ldo t j rising 150 c thermal-shutdown hysteresis t shdn_hyst_ldo 21 c output noise out noise_ldo 10hz to 100khz, v lin = 5v, v lout = 3.3v 150 v rms 10hz to 100khz, v lin = 5v, v lout = 2.5v 125 10hz to 100khz, v lin = 5v, v lout = 1.2v 90 10hz to 100khz, v lin = 5v, v lout = 0.9v 80 b attery impedance measurement swout allowed supply range v swout 2 5.5 v swout uvlo u vloswout falling edge 1.92 2 v swout uvlo hysteresis u vlohyst hysteresis 30 mv v cc impedance test current range i bim_cur programmable current source with step change of 2x 250 8000 a v cc impedance test current accuracy i bim_acc v cc > 1.2v -10 10 % v cc input divider resistance r vcc v cc measure enabled 1.5 m? measurable v cc voltage range v cc_fs allowed v cc voltages range for sar adc operation 1.2 3.6 v v cc voltage resolution lsb v cc_lsb 10.2 mv max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) maxim integrated 8 electrical characteristics (continued) parameter symbol conditions min typ max units worst-case accuracy of single v cc measurement v cc_acc v cc = 1.2v -72 +72 mv v cc = 3.6v -100 +100 worst-case accuracy of differential v cc measurement v cc_acc_diff v cc1 C v cc2 = 100mv -22 +22 % v cc1 C v cc2 = 1.0v -3.5 +3.5 v cc voltage wait time accuracy t wait_acc 10ms, 100ms, 1s programmable t wait -10 +10 % sar adc v cc voltage conversion time t conv actual full v cc measurement time is t wait + t conv 120 s m onitor m ultiplexer swin to mon switch resistance r mon_swin v swin > 1.8v, i load = 2ma 80 120 ? swout/bin/hvin/ hvout/lin to mon switch resistance r mon_hv sensed pin voltage > 1.8v, i load = 500a 400 ? lout/bout to mon switch resistance r mon_lv sensed pin voltage > 0.9v, i load = 500a 500 ? bbm time t bbm anytime monctr[2:0] changed 80 s pulldown resistance r mon_pd monhiz = 0 100 k? uvlo/por input voltage range v vcc 1.8 5.5 v bin uvlo threshold rising v th_bin_rise 1.68 1.73 1.77 v bin uvlo threshold falling v th_bin_falling 1.66 1.71 1.75 v lin uvlo threshold rising v th_lin_rise 1.64 1.68 1.72 v lin uvlo threshold falling v th_lin_falling 1.62 1.66 1.7 v por falling v th_por_falling seal mode 0.76 1.21 v no seal mode 1.55 1.66 1.77 v por rising v th_por_rising seal mode 1.27 1.71 v no seal mode 1.58 1.69 1.8 v max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = -40c to +85c, all registers in their default state, unless otherwise noted. typical values are at t a = +25c.) (note 2) note 2: all devices are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design. note 3: f scl must meet the minimum clock low time plus the rise/fall times. note 4: the maximum t hd:dat has to be met only if the device does not stretch the low period (t low ) of the scl signal. maxim integrated 9 electrical characteristics (continued) parameter symbol conditions min typ max units dig ital signals (v cc = 1.8v to 5.5v , unless otherwise noted. typical values are at v cc = 2.7v .) input logic-high (sda, scl,swen,kin, ben,mpc,len,hven) v ih no seal mode 1.4 v input logic-low (sda, scl,swen,kin, ben,mp,len,hven) v il no seal mode 0.45 v no seal mode, v cc 2.7v 0.5 v input logic-high, seal mode (sda, scl, kin, mpc) v ih_seal seal mode 4.1 v seal mode, v cc 2.7v 2.2 v input logic-low, seal mode (sda, scl, kin, mpc) v il_seal seal mode 0.5 v output logic-low (sda, rst, kout) v ol i ol = 4ma 0.4 v scl clock frequency f scl 0 400 khz kin pullup resistance r kin 210 k? bus free time between a stop and start condition t buf 1.3 s start condition (repeated) hold time t hd:sta (note 3) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (note 4) 0 0.9 s data setup time t su:dat 100 ns setup time for stop condition t su:sto 0.6 s spike pulse widths suppressed by input filter t sp 50 ns max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = +25c, all registers in their default state, unless otherwise noted.) maxim integrated 10 typical operating characteristics 0 2 4 6 8 1 0 - 4 0 - 1 5 1 0 3 5 6 0 8 5 i q ( a ) te m pe r a tur e ( c ) t o t a l q u i es c e n t curr e n t vs . t e m pe r a t ur e t o c 0 1 h ve n = s w e n = b e n = l e n = 0 h ve n = s w e n = be n = l e n = 1 , l d o u v l o s e l = 0 m ax 1475 0 h ve n = s w e n = be n = l e n = 1 , l d o u v l o s e l = 1 0 2 4 6 8 10 1.8 2.8 3.8 4.8 5.8 i q (a) v cc (v) total quiescent current vs. v cc toc02 hven = swen = ben = len = 1, v lout = 1.7v t a = +25 c t a = +85 c t a = - 40 c ldouvlosel = 1 ldouvlosel = 0 0 1 2 3 4 1.8 2.8 3.8 4.8 5.8 i q (a) v cc (v) total quiescent current vs. v cc toc03 hven = swen = ben = len = 0 t a = +25 c t a = +85 c t a = - 40 c 0 20 40 60 80 100 0.001 0.01 0.1 1 10 100 1000 efficiency (%) i b2out (ma) buck efficiency vs. load toc4 v cc = 2.7v v cc = 3.7v 0 20 40 60 80 100 0.001 0.01 0.1 1 10 100 1000 efficiency (%) i hvout (ma) buck - boost efficiency vs. load toc7 v cc = 3.7v v cc = 2.7v i hvout = 10ma 1 . 1 8 1 . 1 9 1 . 2 1 . 2 1 1 . 2 2 0 2 0 4 0 6 0 8 0 1 0 0 v b o u t ( v ) i b o u t ( m a ) v b o u t v s . l o a d t o c 5 v c c = 3 . 7 v v c c = 2 .7 v 50 60 70 80 90 100 1.8 2.8 3.8 4.8 5.8 efficiency (%) v cc (v) buck - boost efficiency vs. v cc toc8 i hvout = 10ma 50ma/div toc6 100 s/div buck transient response v bout 50mv/div i bout 3.2 3.225 3.25 3.275 3.3 3.325 0 20 40 60 80 100 v hvout (v) i hvout (ma) v hvout vs. load toc9 v cc = 2.7v v cc = 3.7v max14720/MAX14750 power-management solution www.maximintegrated.com
(v cc = v bin = v lin = v hvin = v swin = 2.7v, t a = +25c, all registers in their default state, unless otherwise noted.) maxim integrated 11 typical operating characteristics (continued) 50ma/div toc10 100 s/div buck - boost transient response v hvout 50mv/div i hvout 1 v / d i v t o c 1 3 1 0 0 s / d i v l d o l i n e t r a n s i e n t ( v l i n c h a n g e d fr o m 2 v t o 3 v ) v l o u t 2 0 m v / d i v v l i n 1 v / d i v t o c 1 4 1 0 0 s / d i v l d o l i n e t r a n s i e n t ( v l i n c h a n g e d fr o m 1 . 7 5 v t o 2 . 7 5 v , i l o u t = 1 0 m a v l o u t 2 0 0 m v / d i v v l i n 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 1 . 8 2 . 8 3 . 8 4 . 8 5 . 8 r o n ( ( ? ) v s w i n ( v ) p o w e r s w i t ch on - r es i s t anc e vs . v s w i n t o c 1 5 t a = + 8 5 c i s w o u t = 200 m a t a = + 2 5 c t a = - 4 0 c 1 . 5 1 . 7 5 2 2 . 2 5 2 . 5 - 4 0 - 1 5 1 0 3 5 6 0 8 5 fr e q u e nc y ( m h z ) te m pe r a tur e ( c ) buck s w i t ch i n g f r e q u e nc y vs . t e m pe r a t ur e t o c 1 6 v c c = 3 . 7 v v c c = 2 . 7 v i b o u t = 10 m a 1.75 1.775 1.8 1.825 1.85 0 20 40 60 80 100 v b1out (v) i b1out (ma) v lout vs. load toc11 v cc = 2.7v, 3.7v 50ma/div toc12 100 s/div ldo load transient v lout 200mv/div i lout max14720/MAX14750 power-management solution www.maximintegrated.com
maxim integrated 12 bump confgurations bump description max 14720 top view ( bump side down ) wlp ( 2 . 26 mm x 2 . 14 mm ) e d c b a 1 2 3 4 5 hvout hvolx hvilx hvin kout scl gnd kin rst cap sda gnd gnd mpc swout mon gnd gnd v cc swin bin blx bout lin lout max 14750 top view ( bump side down ) wlp ( 2 . 26 mm x 2 . 14 mm ) e d c b a 1 2 3 4 5 hvout hvolx hvilx hvin hven scl gnd swen len cap sda gnd gnd ben swout mon gnd gnd v cc swin bin blx bout lin lout bump name function max14720 MAX14750 a1 a1 bin buck regulator input (must be connected to hvin on the board). bypass with a 1f capacitor to gnd. a2 a2 blx buck regulator switch a3 a3 bout buck regulator output. bypass with a 10f capacitor to gnd. a4 a4 lin ldo input. bypass with a 1f capacitor to gnd. a5 a5 lout ldo output. bypass with a 1f capacitor to gnd. b1 b1 mon monitor multiplexer output b2, b3, c2, c3, d2 b2, b3, c2, c3, d2 gnd ground b4 b4 v cc power supply input b5 b5 swin power switch input. swin v cc c1 c1 sda open-drain i 2 c serial data input/output c4 mpc multipurpose control input c4 ben active-high buck regulator enable input max14720/MAX14750 power-management solution www.maximintegrated.com
note: all capacitance values listed in this document refer to effective capacitance. be sure to specify capacitors that will meet these requirements under typical system operating conditions taking into consideration the effects of voltage and temperature. maxim integrated 13 bump description (continued) block diagram max 14 720 max 14750 control buck - boost buck ldo switch monitor uvlo bump name function max14720 MAX14750 c5 c5 swout power switch output. bypass with a 100f capacitor to gnd for battery impedance measurement. d1 d1 scl i 2 c serial clock d3 kin key input. active-low button monitor with internal 210k? pullup. d3 swen active-high power switch enable input d4 rst active-low, open-drain reset output d4 len active-high linear regulator enable input d5 d5 cap internal power decoupling. bypass with a 0.1f capacitor to gnd. e1 e1 hvout buck-boost regulator output. bypass with a 10f capacitor to gnd. e2 e2 hvolx buck-boost regulator boost switch e3 e3 hvilx buck-boost regulator buck switch e4 e4 hvin buck-boost regulator input (must be connected to bin on the board). bypass with a 1f capacitor to gnd. e5 kout key output. active-low, open-drain buffered copy of kin. e5 hven active-high buck-boost regulator enable input max14720/MAX14750 power-management solution www.maximintegrated.com
detailed description power regulation the max14720/MAX14750 include a buck-boost regulator, a synchronous buck regulator, a low quiescent current linear regulator, and a power switch with integrated battery monitoring. burst mode operation of the switching regulators provides excellent light-load efficiency and allows the switching regulators to run continuously without significant energy cost. the buck-boost regulator in the devices is suitable for applications (such as low-power display biasing) that need the voltage present continuously while running from a battery. the buck-boost regulator can also operate in a current-limited mode to reduce current surges to the supply. the current-limiting is implemented by dividing down the frequency of the switching and is dependent on the ratio of the input-to-output voltage. step-down operation is not allowed when current-limiting is active. uvlo in addition to the internal power-on reset (por) circuit, the devices also have two uvlo circuits that monitor the voltages on bin and lin pin to ensure that input voltages are sufficient for proper operation. it is required that the boost and buck-boost are powered from the same voltage so they share a uvlo on the bin pin. the ldo has its own uvlo on the lin pin. the uvlo circuits are disabled when the blocks are not enabled to reduce the quiescent current. the devices provide the ability to select which of the two uvlos are used so that applications with bin and lin tied to the same supply can share a single uvlo to reduce quiescent current. the selection is made in the uvlocfg register and the effects of the different settings are shown in the table 1 . in the max14720, if there is a fault in a block that is enabled by the sequencer (every _seq[2:0] option except 000, 110 or 111) the part will transition to the shutdown and then the off state. the part will remain off until the next button press. after the button press it will wait for the fault to clear before beginning the power on sequence. a fault is any condition that causes the block to turn off when it should be enabled, such as a uvlo condition or thermal shutdown. output discharge the regulators include circuitry to discharge their outputs. active discharge applies a current sink, while passive discharge applies a load resistor. the active discharge is enabled during hard reset, or for 10ms as the part enters the off/seal mode. it can also be activated in the on state by a register bit when the regulator is disabled. passive discharge is applied in the off/seal mode if the glbpasdsc bit is set and can also be applied in the on state by a register bit when the regulator is disabled. power on/off and reset control the MAX14750 provides individual enable pins for each of the primary functions, while the max14720 includes a push-button monitor and sequencing controller. figure 1 shows the basic flow diagram for the power-management control inside the max14720. each primary function of the max14720 can be automatically enabled by the sequencing controller. the functions can default to be controlled by the i 2 c configuration registers. the default state is determined by the factory configuration. see i 2 c register descriptions section for more information. table 1. u v lo configuration figure 1. power state diagram for max14720 maxim integrated 14 uvlocfg bbbuvlosel ldouvlosel bin uvlo lin uvlo 0x00 lin lin disabled enabled 0x01 lin bin enabled enabled 0x02 bin lin enabled enabled 0x03 bin bin enabled disabled t r s t d e l a y 1 0 m s d e l a y kin = 0 > 1 0 s , or i 2 c c m d = 0 > 4 0 0 m s p ow e r s e qu e n c i n g on s h u td ow n h ol d r s t l ow a c ti v e l y d i s c h a r ge ou t p u ts p ow e r - on r es e t otp t b o o t d e l a y off ( se a l m od e ) m a x 1472 0 kin max14720/MAX14750 power-management solution www.maximintegrated.com
when the device begins the shutdown process, reset is driven low, all functions are disabled and outputs are actively discharged. then, 10ms later, the device will be in the off state (seal mode) where all functions are disabled except for the power button monitor. power sequencing (max14720 only) the sequencing of the voltage regulators during power- on is configurable. each regulator can be configured to be turned on at one of four points during the power-on process. the four points are: t boot after the power-on event, after the rst signal is released, or at two points in between. the two points in between are fixed proportionally to the duration of the por process, but the overall time of the reset delay is configurable at 80ms, 120ms, 220ms, and 420ms. (note that the actual turn-on time of some converters may be limited by the soft-starting of the output.) figure 2 shows the timing relationship. additionally, the regulators can be preselected to default off and can be turned on with an i 2 c command after reset is released. battery impedance measurement the max14720 contains circuitry to measure the impedance of the power supply. to perform this measurement, swin must be connected to v cc , with no capacitor present on the battery-side; all loads draw their power from the power-switch output (see typical application circuits ). by default, the power switch is configured with a soft-start current limit that prevents potential high current drawn from the battery. this soft-start lasts 60ms after the power switch is turned on. during battery measurement, the impedance measurement circuitry will open the power switch and record the voltage at the input to the switch before and after a current load is applied. during the measurement, the system must rely on the energy stored in the capacitor attached to the output of the switch for operation. if the swout voltage falls below swout uvlo threshold, the battery measurement is immediately aborted and the power switch closes. the parameters of the current load and the timing of the pulse are specified in registers battime(0x0d) and batcfg(0x0e) when the measurement is requested and the results are presented in registers batv(0x0f), batocv(0x10), and batlcv(0x11) (see figure 3). i 2 c interface the devices use the two-wire i 2 c interface to communicate with the host microcontroller. the configuration settings and status information provided through this interface are detailed in the register descriptions. i 2 c addresses the registers of the devices are accessed through the slave address of 010101ax (a is configurable by otp). figure 2. reset sequence programming (max14720) figure 3. battery impedance measurement maxim integrated 15 % of t rst 010 100 111 * power on reset rst _ out ** _ seq *** 0 % 25 % 50 % 100 % t boot 011 * output controlled by state of register enable bits . ** _ out = hvout , bout , lout , or swout *** _ seq = boostseq , buckseq , ldoseq , or swseq t rst wait bcvtm measure bcv take measurement bcvtm = 0 wait 1ms reset: bcv, ocv, lcv no open switch wait ocvtm measure ocv ocvtm = 0 no yes lcvtm = 0 yes no enable load wait lcvtm measure lcv disable load wait lcvtm* yes close switch wait 1ms done *skipped if lcvdly2skip = 1 max14720/MAX14750 power-management solution www.maximintegrated.com
i 2 c register map note: all registers reset to default value on hard and soft reset. reserved bits: must not be modified from their default states to ensure proper operation. bolded names: bits default value can be factory configured by otp. bolded bits with asterisk are set by otp only. *read-only **bits autoreset at the end of impedance measurement (either completed or aborted). maxim integrated 16 register address register name b7 b6 b5 b4 b3 b2 b1 b0 0x00 chipid chipid[7:0]* 0x01 chiprev chiprev[7:0]* 0x02 reserved reserved 0x03 boostcdiv clkdiven clkdivset[6:0] 0x04 boostiset boostiset[2:0] 0x05 boostvset boostvset[4:0] 0x06 boostcfg boostseq[2:0]* boosten[1:0] - boostemi boostind 0x07 buckvset buckvset[5:0] 0x08 buckcfg buckseq[2:0]* bucken[1:0] buckmd[1:0] buckfst 0x09 buckiset buckiset[2:0] buckcfg buckind buckhysoff buckminot buckinteg 0x0a ldovset ldovset[4:0] 0x0b ldocfg ldoseq[2:0]* ldo pasdsc ldo actdsc ldoen[1:0] ldomode 0x0c switchcfg swseq[2:0]* swen[1:0] swsoftstart 0x0d battime bcvtm[1:0] ocvtm[1:0] lcvtm[1:0] 0x0e batcfg bia** bimabort** lcvdly2skip batimpcur[2:0] 0x0f batbcv bcv[7:0]* 0x10 batocv ocv[7:0]* 0x11 batlcv lcv[7:0]* 0x12-0x18 reserved reserved 0x19 moncfg monen monhiz monctr[2:0] 0x1a bootcfg pwrrstcfg[3:0]* sftrstcfg* pfnpudcfg* bootdly[1:0]* 0x1b pinstat kin/swen kout/hven mpc/ben rst/len 0x1c bbbextra boost hysoff boostpasdsc boost actdsc buckpasdsc buckactdsc buckfscl 0x1d handshk startoff* glbpasdsc* stayon 0x1e uvlocfg bbbuvlosel* ldo uvlosel 0x1f pwroff pwroffcmd[7:0] 0x20 0x2b otpmap programmed default otp values max14720/MAX14750 power-management solution www.maximintegrated.com
i 2 c register descriptions table 2. chipid register (0x00) table 3. chiprev register (0x01) table 4. boostcdiv register (0x03) table 5. boostiset register (0x04) maxim integrated 17 address: 0x00 (read-only) bit 7 6 5 4 3 2 1 0 name chipid[7:0] chip_id[7:0] chip_id[7:0] bits show information about the version of the max14720/MAX14750. address: 0x01 (read-only) bit 7 6 5 4 3 2 1 0 name chiprev[7:0] chiprev[7:0] chiprev[7:0] bits show information about the revision of the max14720/MAX14750 silicon. address: 0x03 bit 7 6 5 4 3 2 1 0 name clkdiven clkdivset[6:0] clkdiven boost current-limited output mode enable this allows the boost regulator to be operated in a current limited output mode. 0: normal operation, full output current capability 1: divided clock current limited mode when the clock divider is enabled, the boost is operated with a fxed peak current limit and programmable frequency. the peak current is set by boostiset[2:0] and the switching frequency is determined by clkdivset[6:0]. the regulator will stop switching when the voltage is above the set point and will only run when the voltage is below the output setting. this mode can only be enabled once the output voltage is set higher than the input voltage. clkdivset[6:0] current-limited boost clock divider setting when the current limited mode is enabled, the frequency of the boost regulator in current limited mode will be the frequency of the oscillator divided by the value of (10 + clkdivset[6:0]). the range is f osc /10 to f osc /137. address: 0x04 bit 7 6 5 4 3 2 1 0 name boostiset[2:0] boostiset[2:0] buck-boost peak current-limit setting 000: 0 (minimum on-time) 001: 50ma 010: 100ma 011: 150ma 100: 200ma 101: 250ma 110: 300ma 111: 350ma max14720/MAX14750 power-management solution www.maximintegrated.com
table 6. boost v set register (0x05) table 7. boostcfg register (0x06) maxim integrated 18 address: 0x05 bit 7 6 5 4 3 2 1 0 name boostvset[4:0] boostvset[4:0] boost output voltage setting. this setting is internally latched and can change only when boost is disabled. 2.5v to 5.0v, linear scale, 100mv increments 000000 = 2.5v 000001 = 2.6v 011001 = 5.0v > 011001 = 5.0v address: 0x06 bit 7 6 5 4 3 2 1 0 name boostseq[2:0] (read-only) boosten[1:0] boostemi boostind boostseq[2:0] boost enable confguration (read-only) 000 = disabled 001 = reserved 010 = enabled at 0% of boot/por process delay control 011 = enabled at 25% of boot/por process delay control 100 = enabled at 50% of boot/por process delay control 101 = reserved 110 = controlled by hven (MAX14750) 111 = controlled by boosten [1:0] after 100% of boot/por process delay control (max14720) boosten[1:0] boost enable confguration (effective only when boostseq[2:0] == 111) 00 = disabled. active discharge behavior depends on boostactdsc. 01 = enabled 10 = enabled when mpc is high 11 = reserved boostemi boost emi reduction. dampens ringing of the inductor when in discontinuous mode 0 = emi damping active (improve emi) 1 = emi damping disabled (improve effciency) boostind boost inductance select 1 = inductance is 3.3h 0 = inductance is 4.7h max14720/MAX14750 power-management solution www.maximintegrated.com
table 8. buck v set register (0x07) table 9. buckcfg register (0x08) maxim integrated 19 address: 0x07 bit 7 6 5 4 3 2 1 0 name buckvset[5:0] buckvset[5:0] buck output voltage setting this setting is internally latched and can change only when buck is disabled. 1.0v to 2.0v, linear scale, 25mv increments 000000 = 1.000v 000001 = 1.025v 101000 = 2.0v > 101000 = 2.0v address: 0x08 bit 7 6 5 4 3 2 1 0 name buckseq[2:0] (read-only) bucken[1:0] buckmd[1:0] buckfst buckseq[2:0] buck enable confguration (read-only) 000 = disabled 001 = reserved 010 = enabled at 0% of boot/por process delay control 011 = enabled at 25% of boot/por process delay control 100 = enabled at 50% of boot/por process delay control 101 = reserved 110 = controlled by ben (MAX14750) 111 = controlled by bucken [1:0] after 100% of boot/por process delay control bucken[1:0] buck enable confguration (effective only when buckseq[2:0] == 111) 00 = disabled. active discharge behavior depends on buckactdsc. 01 = enabled 10 = enabled when mpc is high 11 = reserved buckmd[1:0] buck mode select 00 = burst mode 01 = forced pwm mode 10 = forced pwm mode when mpc is high 11 = reserved buckfst buck fast start 0 = normal startup current limit 1 = double the startup current to reduce the startup time by half max14720/MAX14750 power-management solution www.maximintegrated.com
table 10. buckiset register (0x09) table 11. ldo v set register (0x0a) maxim integrated 20 address: 0x09 bit 7 6 5 4 3 2 1 0 name buckiset[2:0] buckcfg buckind buckhysoff buckminot buckinteg buckiset[2:0] buck peak current limit setting 000: 50ma 001: 100ma 010: 150ma 011: 200ma 100: 250ma 101: 300ma 110: 350ma 111: 400ma buckcfg buck confguration 0 = set to 0 for burst mode 1 = set to 1 for fpwm mode buckind buck inductance select 0 = inductance is 2.2h 1 = inductance is 4.7h buckhysoff buck hysteresis off 0 = enable comparator hysteresis 1 = disable comparator hysteresis (recommended to reduce voltage ripple) buckminot buck minimum on-time 0 = enable deglitch delay on comparator for better effciency 1 = disable deglitch delay on comparator to minimize voltage ripple buckinteg buck integrate 0 = helps stabilize the buck regulator for high currents with small output capacitor 1 = better load regulation at high current (recommended for output capacitance > 6f) address: 0x0a bit 7 6 5 4 3 2 1 0 name ldovset[4:0] ldovset[4:0] ldo output voltage setting 0.9v to 4v, linear scale, 100mv increments 00000 = 0.9v 00001 = 1.0v 10000 = 2.5v 11111 = 4.0v max14720/MAX14750 power-management solution www.maximintegrated.com
table 12. ldocfg register (0x0b) maxim integrated 21 address: 0x0b bit 7 6 5 4 3 2 1 0 name ldoseq[2:0] (read-only) ldopasdsc ldoactdsc ldoen[1:0] ldomode ldoseq[2:0] ldo enable confguration (read-only) 000 = disabled 001 = enabled always when bat/sys is present 010 = enabled at 0% of boot/por process delay control 011 = enabled at 25% of boot/por process delay control 100 = enabled at 50% of boot/por process delay control 101 = disabled 110 = controlled by len (MAX14750) 111 = controlled by ldoen[1:0] after 100% of boot/por process delay control ldopasdsc ldo passive discharge control 0: ldo output will be discharged only entering off and hard-reset modes. 1: ldo output will be discharged only entering off and hard-reset modes and when the enable is low. ldoactdsc ldo active discharge control 0: ldo output will be actively discharged only entering off and hard-reset modes. 1: ldo output will be actively discharged only entering off and hard-reset modes and when the enable is low. ldoen[1:0] ldo enable confguration (effective only when ldoseq[2:0] == 111) 00 = disabled 01 = enabled 10 = enabled when mpc is high 11 = reserved ldomode ldo mode control 0 = normal ldo operating mode 1 = load switch mode. fet is either fully on or off depending on the state of ldoen. when fet is on, the output is unregulated and is not affected by uvlos control block. this setting is internally latched and can change only when the ldo is disabled. max14720/MAX14750 power-management solution www.maximintegrated.com
table 13. switchcfg register (0x0c) table 14. battime register (0x0d) maxim integrated 22 address: 0x0c bit 7 6 5 4 3 2 1 0 name swseq[2:0] (read-only) swen[1:0] swsoftstart swseq[2:0] sw enable confguration (read-only) 000 = disabled 001 = enabled always when bat/sys is present 010 = enabled at 0% of boot/por process delay control 011 = enabled at 25% of boot/por process delay control 100 = enabled at 50% of boot/por process delay control 101 = disabled 110 = controlled by swen (MAX14750) 111 = controlled by swen[1:0] after 100% of boot/por process delay control swen sw enable confguration (effective only when swseq[2:0] == 111) 00 = disabled 01 = enabled 10 = enabled when mpc is high 11 = reserved swsoftstart sw softstart 0 = no soft-start is present when the switch is enabled. 1 = current limit of 25ma (typ) is ensured for 60ms when the switch is enabled. address: 0x0d bit 7 6 5 4 3 2 1 0 name bcvtm[1:0] ocvtm[1:0] lcvtm[1:0] bcvtm[1:0] battery cell voltage timing 00: skip battery measurement 01: take battery measurement after 10ms delay 10: take battery measurement after 100ms delay 11: take battery measurement after 1000ms delay ocvtm[1:0] battery open cell voltage timing if this step is skipped, lcv measurement will be taken with switch closed 00: skip ocv measurement 01: take ocv measurement after 10ms delay 10: take ocv measurement after 100ms delay 11: take ocv measurement after 1000ms delay lcvtm[1:0] battery loaded cell voltage timing 00: skip lcv measurement 01: take lcv measurement after 10ms delay 10: take lcv measurement after 100ms delay 11: take lcv measurement after 1000ms delay max14720/MAX14750 power-management solution www.maximintegrated.com
table 15. batcfg register (0x0e) table 16. bat v register (0x0f) maxim integrated 23 address: 0x0e bit 7 6 5 4 3 2 1 0 name bia bimabort lcvdly2skip batlmpcur[2:0] bia battery impedance active write 1 to start battery impedance measurement. if the measurement is already running, the write is ignored. bit will remain high until the measurement is completed. 0: battery impedance measurement is not ongoing 1: battery impedance measurement is ongoing bimabort battery impedance measurement skip write 1 to immediately abort the battery impedance measurement 0: battery impedance measurement is aborted 1: battery impedance measurement is not aborted yet lcvdly2skip write 1 to skip the second delay time (equal again to lcvtm) after lcv measurement is taken. this second delay time allows v cc to recover its unloaded value before closing the power switch again. 0: wait second delay time 1: skip second delay time batimpcur [2:0] battery impedance current 000: 0 001: 250a 010: 500a 011: 1ma 100: 2ma 101: 4ma 110: 8ma 111: reserved address: 0x0f (read-only) bit 7 6 5 4 3 2 1 0 name bcv[7:0] bcv[7:0] battery voltage measurement result 8-bit battery voltage measurement: v cc = [ 2.6 * (bcv[7:0]/255) + 1.1 ] v if bcvtm[2:0] = 00, bcv[7:0] = 0000 0000. if error occurs or the measurement is aborted, bcv[7:0] =1111 1111. max14720/MAX14750 power-management solution www.maximintegrated.com
table 17. batoc v register (0x10) table 18. batlc v register (0x11) table 19. moncfg register (0x19) maxim integrated 24 address: 0x10 (read-only) bit 7 6 5 4 3 2 1 0 name ocv[7:0] ocv[7:0] battery voltage measurement result 8-bit battery voltage measurement: v cc = [2.6 x (ocv[7:0]/255) + 1.1] v if ocvtm[2:0] = 00, ocv[7:0] =0000 0000. if error occurs or the measurement is aborted, ocv[7:0] =1111 1111. address: 0x11 (read-only) bit 7 6 5 4 3 2 1 0 name lcv[7:0] lcv[7:0] battery voltage measurement result 8 bit battery voltage measurement: v cc = [2.6 x ( lcv[7:0]/255) + 1.1] v if lcvtm[2:0] = 00, bcv[7:0] = 0000 0000. if error occurs or the measurement is aborted, lcv[7:0] =1111 1111. address: 0x19 bit 7 6 5 4 3 2 1 0 name monen monthiz monctr[2:0] monen monitor enable 0 = monitor function disabled 1 = monitor function enabled monthiz mon off mode condition 0 = pulled low by a 100k pulldown resistor 1 = hi-z monctr[2:0] mon pin source selection 000 = mon connected to swin 001 = mon connected to swout 010 = mon connected to bin 011 = mon connected to bout 100 = mon connected to hvin 101 = mon connected to hvout 110 = mon connected to lin 111 = mon connected to lout max14720/MAX14750 power-management solution www.maximintegrated.com
table 20. bootcfg register (0x1a) table 21. pinstat register (0x1b) maxim integrated 25 address: 0x1a (read-only) bit 7 6 5 4 3 2 1 0 name pwrrstcfg[4:0] sftrstcfg pfnpudcfg bootdly[1:0] pwrrstcfg [4:0] 0000: pin controlled (MAX14750) 0110: push-button monitor (max14720) sftrstcfg soft reset register default 0 = registers do not reset to default values on soft reset 1 = registers reset to default values on soft reset pfnpudcfg kin pullup/pulldown confguration 0 = pullups and pulldowns on control lines disabled 1 = selective pullups and pulldowns enabled on kin pin bootdly[1:0] boot/por process t reset delay control 00 = 80ms 01 = 120ms 10 = 220ms 11 = 420ms address: 0x1b (read-only) bit 7 6 5 4 3 2 1 0 name (max14720) kin kout mpc rst name (MAX14750) swen hven ben len kin, kout, mpc, rst, swen, hven, ben, len input state 0 = pin low 1 = pin high max14720/MAX14750 power-management solution www.maximintegrated.com
table 22. bbbextra register (0x1c) table 23. h andshk register (0x1d) maxim integrated 26 address: 0x1c bit 7 6 5 4 3 2 1 0 name boosthysoff boostpasdsc boostactdsc 0 buckpasdsc buckactdsc buckfscl boosthysoff boost hysteresis off 0 = enable comparator hysteresis 1 = disable comparator hysteresis (recommended to reduce voltage ripple) boostpasdsc boost passive discharge control 0: boost output will be discharged only when entering off and hard-reset modes. 1: boost output will be discharged only when entering off and hard-reset modes and when boosten is set to 00. boostactdsc boost active discharge control 0: boost output will be discharged only when entering off and hard-reset modes. 1: boost output will be discharged only when entering off and hard-reset modes and when boosten is set to 00. buckpasdsc buck passive discharge control 0: buck output will be discharged only when entering off and hard-reset modes. 1: buck output will be discharged only when entering off and hard-reset modes and when bucken is set to 00. buckactdsc buck active discharge control 0: buck output will be discharged only when entering off and hard-reset modes. 1: buck output will be discharged only when entering off and hard-reset modes and when bucken is set to 00. buckfscl buck force fet scaling (it reduces i q by lowering the nmos power to 20% of the nominal value) 0: fet scaling only enabled during the buck turn-on sequence 1: fet scaling enabled during the buck turn-on sequence and also in the buck active state. address: 0x1d (read-only) bit 7 6 5 4 3 2 1 0 name startoff glbpasdsc stayon startoff start in off 1: the device will start in the off mode. 0: the device begins the power-on sequence after a v cc power on reset. glbpasdsc global passive discharge 0: passive discharge loads are disabled in off mode. 1: passive discharge loads are enabled in off mode. stayon processor handshake this bit is used to ensure that the processor booted correctly. this bit must be set within 5s of power-on to prevent the part from shutting down and returning to the power-off condition. this bit has no effect after being set. 0 = shutdown 5s after power-on 1 = stay on max14720/MAX14750 power-management solution www.maximintegrated.com
table 24. u v locfg register (0x1e) table 25. p wrcfg register (0x1f) maxim integrated 27 address: 0x1e bit 7 6 5 4 3 2 1 0 name bbbuvlosel (read only) ldouvlosel bbbuvlosel buck/buck-boost uvlo select 0: buck and buck-boost are turned off/on according to lin_uvlo thresholds 1: buck and buck-boost are turned off/on according to bin_uvlo thresholds ldouvlosel ldo uvlo select 0: ldo is turned off/on according to lin_uvlo thresholds 1: ldo is turned off/on according to bin_uvlo thresholds address: 0x1f bit 7 6 5 4 3 2 1 0 name pwroffcmd[7:0] pwroffcmd [7:0] power-off command writing 0xb2 to this register will place the part in the off state/seal mode. waking up the device from this mode requires a low pulse on kin. all other codes = do nothing max14720/MAX14750 power-management solution www.maximintegrated.com
i 2 c interface the max14720/MAX14750 contain an i 2 c-compatible interface for data communication with a host controller (scl and sda). the interface supports a clock frequency of up to 400khz. scl and sda require pullup resistors that are connected to a positive supply. start, stop, and repeated start conditions when writing to the max14720/MAX14750 using i 2 c, the master sends a start condition (s) followed by the max14720/MAX14750 i 2 c address. after the address, the master sends the register address of the register that is to be programmed. the master then ends communication by issuing a stop condition (p) to relinquish control of the bus, or a repeated start condition (sr) to communicate to another i 2 c slave. see figure 4. slave address set the read/ write bit high to configure the devices to read mode ( table 26). set the read/ write bit low to configure the max14720/MAX14750 to write mode. the address is the first byte of information sent to the max14720/MAX14750 after the start condition. bit transfer one data bit is transferred on the rising edge of each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start, stop, and repeated start conditions section). both sda and scl remain high when the bus is not active. single-byte w rite in this operation, the master sends an address and two data bytes to the slave device ( figure 5 ). the following procedure describes the single byte write operation: 1) the master sends a start condition 2) the master sends the 7-bit slave address plus a write bit (low) 3) the addressed slave asserts an ack on the data line 4) the master sends the 8-bit register address 5) the slave asserts an ack on the data line only if the address is valid (nak if not) 6) the master sends 8 data bits 7) the slave asserts an ack on the data line 8) the master generates a stop condition s p device slave address - w a 8 data bits write single byte from master to slave from slave to master a register address a scl sda ss rp figure 5. write byte sequence table 26. i 2 c slave addresses address format hex binary 7-bit slave id 0x2a 0101010 write address 0x54 0000 0100 read address 0x55 01010101 figure 4. i 2 c start, stop, and repeated start conditions maxim integrated 28 max14720/MAX14750 power-management solution www.maximintegrated.com
burst w rite in this o peration, the master sends an address and multiple data bytes to the slave device ( figure 6 ). the slave device automatically increments the register address after each data byte is sent, unless the register being accessed is 0x00, in which case the register address remains the same. the following procedure describes the burst write operation: 1) the master sends a start condition 2) the master sends the 7-bit slave address plus a write bit (low) 3) the addressed slave asserts an ack on the data line 4) the master sends the 8-bit register address 5) the slave asserts an ack on the data line only if the address is valid (nak if not) 6) the master sends eight data bits 7) the slave asserts an ack on the data line 8) repeat 6 and 7 n-1 times 9) the master generates a stop condition single byte read in this operation, the master sends an address plus two data bytes and receives one data byte from the slave device ( i2c register descriptions ). the following proce- dure describes the single byte read operation: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nak if not). 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends eight data bits. 10) the master asserts a nack on the data line. 11) the master generates a stop condition. figure 6. burst write sequence figure 7. read byte sequence figure 6 s device slave address - w a 8 data bits - 1 burst write a register address a 8 data bits - n a 8 data bits - 2 a from master to slave from slave to master p figure 7 s sr device slave address - w a device slave address - r read single byte a register address a 8 data bits na from master to slave from slave to master p maxim integrated 29 max14720/MAX14750 power-management solution www.maximintegrated.com
burst read in this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device ( figure 8 ). the following procedure describes the burst byte read operation: 1) the master sends a start condition 2) the master sends the 7-bit slave address plus a write bit (low) 3) the addressed slave asserts an ack on the data line 4) the master sends the 8-bit register address 5) the slave asserts an ack on the data line only if the address is valid (nak if not) 6) the master sends a repeated start condition 7) the master sends the 7-bit slave address plus a read bit (high) 8) the slave asserts an ack on the data line 9) the slave sends eight data bits 10) the master asserts an ack on the data line 11) repeat 9 and 10 n-2 times 12) the slave sends the last eight data bits 13) the master asserts a nack on the data line 14) the master generates a stop condition acknowledge bits data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max14720/MAX14750 generate ack bits. to generate an ack, pull sda low before the rising edge of the ninth clock pulse and hold it low during the high period of the ninth clock pulse ( figure 9 ). to generate a nack, leave sda high before the rising edge of the ninth clock pulse and leave it high for the duration of the ninth clock pulse. monitoring for nack bits allows for detection of unsuccessful data transfers. figure 8. burst read sequence figure 9. acknowledge s sr device slave address - w a device slave address - r burst read a register address a 8 data bits - 1 a a 8 data bits - 3 8 data bits - 2 a 8 data bits - n na from master to slave from slave to master p not acknowledg e acknowledge 12 89 sda scl s maxim integrated 30 max14720/MAX14750 power-management solution www.maximintegrated.com
table 27. register bit default v alues maxim integrated 31 register bits MAX14750a max14720a max14720b boostiset[2:0] 100ma 100ma 100ma boostvset[4:0] 3.3v 3.3v 3.3v bbbuvlosel bin bin bin ldouvlosel lin bin bin buckvset[5:0] 1.2v 1.2v 1.8v buckiset[2:0] 300ma 300ma 300ma buckcfg burst burst burst buckind 2.2h 2.2h 2.2h buckhysoff lower ripple lower ripple lower ripple buckminot lower ripple lower ripple lower ripple buckinteg higher dc accuracy higher dc accuracy higher dc accuracy i2cadd 0101010 0101010 0101011 stayon stay on stay on stay on ldovset[4:0] 1.8v 1.8v 1.8v boostseq[2:0] hven boosten boosten boostind 4.7h 4.7h 4.7h buckseq[2:0] ben 50% 50% buckfst zero zero zero ldoseq[2:0] len 50% ldoen (i 2 c) ldomode ldo ldo load switch swseq[2:0] swen 0% 0% swsoftstart none 25ma (typ) for 60ms 25ma (typ) for 60ms bcvtm[1:0] skip skip skip ocvtm[1:0] skip skip skip lcvtm[1:0] skip skip skip ldopasdsc off off off ldoactdsc off off off batimpcur 0ma 0ma 0ma pwrrstcfg[3:0] pin enable kin kin sftrstcfg hold regs hold regs hold regs pfnpudcfg disabled enabled enabled bootdly[1:0] 80ms 120ms 120ms startoff power on remain off remain off glbpasdsc disabled disabled disabled boosthysoff more effcient more effcient more effcient max14720/MAX14750 power-management solution www.maximintegrated.com
table 28. register default v alues table 27. register bit default v alues (continued) maxim integrated 32 register bits MAX14750a max14720a max14720b boostpasdsc off off off boostactdsc off off off buckpasdsc off off off buckactdsc off off off buckfscl zero zero zero clkdivena disabled disabled disabled clkdivset[6:0] 0 0 0 register address register name default v alues MAX14750a max14720a max14720b 0x00 chipid 0x01 0x01 0x01 0x01 chiprev 0x01 0x01 0x01 0x02 reserved 0x00 0x00 0x00 0x03 boostcdiv 0x00 0x00 0x00 0x04 boostiset 0x02 0x02 0x02 0x05 boostvset 0x08 0x08 0x08 0x06 boostcfg 0xc0 0xe0 0xe0 0x07 buckvset 0x08 0x08 0x20 0x08 buckcfg 0xc0 0x80 0x80 0x09 buckiset 0xa7 0xa7 0xa7 0x0a ldovset 0x09 0x09 0x09 0x0b ldocfg 0xc0 0x80 0xe1 0x0c switchcfg 0xc0 0x41 0x41 0x0d battime 0x00 0x00 0x00 0x0e batcfg 0x00 0x00 0x00 0x0f batbcv 0x00 0x00 0x00 0x10 batocv 0x00 0x00 0x00 0x11 batlcv 0x00 0x00 0x00 0x12 reserved 0x00 0x00 0x00 0x13 reserved 0x00 0x00 0x00 0x14 reserved 0x00 0x00 0x00 0x15 reserved 0x00 0x00 0x00 0x16 reserved 0x00 0x00 0x00 0x17 reserved 0x00 0x00 0x00 0x18 reserved 0x34 0x34 0x34 max14720/MAX14750 power-management solution www.maximintegrated.com
table 28. register default v alues (continued) figure 10. lithium coin cell maxim integrated 33 register address register name default v alues MAX14750a max14720a max14720b 0x19 moncfg 0x00 0x00 0x00 0x1a bootcfg 0x00 0x61 0x61 0x1b pinstat 0x00 0x00 0x00 0x1c bbbextra 0x00 0x00 0x00 0x1d handshk 0x01 0x81 0x81 0x1e uvlocfg 0x02 0x03 0x03 0x1f pwroff 0x00 0x00 0x00 max 32620 b uck - b oost + 3 . 3 v hvin vsys 1 f hvout hvilx hvolx b uck bin 1 f blx bout + 1 . 2 v 10 f 10 f 2 . 2 h v dd12 v ddb ldo lin 1 f lout 1 f + 1 . 8 v v dd18 vrtc switch + 2 . 0 v to + 3 . 6 v swout 100 f vsys swin vbat control kin kout mpc rst gnd v cc vbat mon adc scl scl sda sda 0 . 1 f cap rst mpc key max 14720 a 4 . 7 h typical application circuits max14720/MAX14750 power-management solution www.maximintegrated.com
figure 11. removable li+ rechargeable maxim integrated 34 m a x 3262 0 b u c k - b oo s t + 3 . 3 v h v i n 1 f h v ou t h v i l x h v o l x b u c k b i n 1 f b l x b ou t + 1 . 8 v 1 0 f 1 0 f 2 . 2 h v d d 1 8 v d d b l d o l i n 1 f l o u t 1 f v d d 1 2 v r tc s w i tc h s w ou t 1 f vs y s c on tr ol k i n k o u t m p c r s t gn d v c c m on a d c s c l s c l s d a s d a 0 . 1 f c a p r s t m p c k e y m a x 1472 0 4 . 7 h + 2 . 7 v to + 4 . 35 v vb a t 1 f s w i n + 1 . 2 v vb a t 0 . 1 f + 1 . 8 v typical application circuits (continued) max14720/MAX14750 power-management solution www.maximintegrated.com
figure 12. always-on coin cell maxim integrated 35 m a x 32620 b uc k - b oo s t + 3 . 3 v h v i n 1 f h v ou t h v i l x h v ol x b uc k b i n 1 f 1 0 f v dd b l d o l i n 1 f l ou t v dd 1 8 v r tc c on tr ol s w e n h ve n be n l e n gn d v c c m on a d c s c l s c l s d a s d a 0 . 1 f c a p h ve n s w e n m a x 14750 a 4 . 7 h + 1.8v to + 3 . 6 v vba t 1 f s w i n vba t 0 . 1 f b l x b ou t 1 0 f 2 . 2 h v dd 1 2 + 1 . 2 v 1 f + 1 . 8 v s w ou t 1 0 f vsy s s w i tc h typical application circuits (continued) max14720/MAX14750 power-management solution www.maximintegrated.com
figure 13. companion li+ rechargeable maxim integrated 36 m a x 32620 b uc k - b oo s t + 3 . 3 v h v i n vsy s 1 f h v ou t h v i l x h v ol x b uc k b i n 1 f b l x b ou t 1 0 f 1 0 f 2 . 2 h v dd 1 8 v dd b l d o l i n 1 f l ou t 1 f + 1 . 2 v v dd 1 2 v r tc s w ou t 1 f s w 1 . 8 v c on tr ol s w e n h ve n be n l e n gn d v c c m on a d c s c l s c l s d a s d a 0 . 1 f c a p s w e n m a x 14750 4 . 7 h + 2 . 7 v to + 5 v s w i n 1 f + 1 . 8 v s w i tc h + 1 . 8 v 0 . 1 f vsy s vb u s vsy s 1 . 8 v typical application circuits (continued) max14720/MAX14750 power-management solution www.maximintegrated.com
+denotes a lead(pb)-free/rohs-compliant package. *future productcontact factory for availability. t = tape and reel. maxim integrated 37 ordering information chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp ran ge pin-pac kage max14720 aewa+ -40c to +85c 25 wlp max14720aewa+t -40c to +85c 25 wlp max14720bewa+* -40c to +85c 25 wlp max14720bewa+t* -40c to +85c 25 wlp MAX14750 aewa+ -40c to +85c 25 wlp MAX14750aewa+t -40c to +85c 25 wlp MAX14750bewa+* -40c to +85c 25 wlp MAX14750bewa+t* -40c to +85c 25 wlp pac kage type pac kage code outline no. land pattern no. 25 wlp w252m2+1 21-0788 refer to application note 1891 max14720/MAX14750 power-management solution www.maximintegrated.com
? 2016 maxim integrated products, inc. 38 revision history revision number revision date description pages changed 0 12/15 initial release 1 2/16 worst-case accuracy of single v cc measurement spec updated in electrical characteristics table 8 2 8/16 general updates 16, 21, 31C33 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max14720/MAX14750 power-management solution for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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